﻿@inproceedings{
HLS:Latch96,
   Author = {Lin, Y. and Wu, T.},
   Title = {Storage optimization by replacing some flip-flops with latches},
   BookTitle = {Euro-DAC },
      Year = {1996} }

@inproceedings{
misc:Mul,
   Author = {Carl Lemonds},
   Title = {A High Throughput 16 by 16 Bit Multiplier for DSP Cores},
   BookTitle = {IEEE International Symposium on Circuits and Systems},
      Year = {1996} }

@inproceedings{
HLS:Latch01,
   Author = {W. Yang and I. Park and C. Kyung},
   Title = {Low-power high-level synthesis using latches},
   BookTitle = {ASP-DAC},
   Abstract = {High-level synthesis using latches has many merits in power, area and even in speed. But latches cannot be read and written at the same time and usually requires two-phase non-overlapping dock that is unpleasant choice for short-term design. In this paper we propose a storage allocation method that makes it possible to use latches as storage elements in single clocking scheme. The proposed method modifies the lifetime of variables slightly so that it can be applied to any high-level synthesis systems with small modification. The experimental results show 39-65% reduction in power consumption within almost the same area compared to the conventional power management scheme using clock gating},
   Keywords = {clocks
flip-flops
high level synthesis
low-power electronics
storage allocation
clock gating
high-level synthesis systems
latches
low-power high-level synthesis
power consumption
power management scheme
single clocking scheme
storage allocation method
storage elements},
   Year = {2001} }


@inproceedings{
hls-old,
   Author = {Paulin, P.G and Knight, J.P. and et. al.},
   Title = { Force-directed scheduling for the behavioral synthesis of ASICs},
   BookTitle = {IEEE TCAD},
      Year = {1989} }

@book{
mc-book,
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@misc{
URL:VX,
	author = {Synopsys},
	title = {PrimeTime {VX}},
	howpublished = "\url{http://www.synopsys.com/}"
}

@inproceedings{
HLS:Yibo09,
    author = {Y. Chen and Y. Xie},
    title = {Tolerating Process Variations in High-Level Synthesis Using Transparent Latches},
    booktitle = {ASPDAC},
    year = {2009}
}

@inproceedings{
HLS:Greg09,
    author = {G. Lucas and S. Cromar and D. Chen},
    title = {{FastYield}: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization},
    booktitle = {ASPDAC},
    year = {2009}
}

@inproceedings{
HLS:Jung07,
    author = {J. Jung and T. Kim},
    title = {Timing Variation-Aware High Level Synthesis},
    booktitle = {ICCAD},
    year = {2007}
}

@inproceedings{
HLS:Wang08,
    author = {F. Wang and G. Sun and Y. Xie},
    title = {A Variation Aware High Level Synthesis Framework},
    booktitle = {DATE},
    year = {2008}
}

@inproceedings{
HLS:Wang082,
    author = {F. Wang and \emph{et al.}},
    title = {Variability-driven module selection with joint design time optimization and post-silicon tuning},
    booktitle = {ASPDAC},
    year = {2008}
}

@misc{
URL:freepdk,
	author = {NCSU},
	title = {45nm {FreePDK}},
	howpublished = "\url{http://www.eda.ncsu.edu/wiki/FreePDK}"
}

@misc{
URL:IVM,
	title = {{IVM}},
	howpublished = "\url{http://www.crhc.illinois.edu/ACS/tools/ivm/about.html}"
}

@inproceedings{
HLS:Khouri02,
    author = {K. Khouri and N. Jha},
    title = {Leakage power analysis and reduction during behavioral synthesis},
    booktitle = {IEEE Transaction on VLSI},
    year = {2002}
}

@inproceedings{
HLS:Tang05,
    author = {X. Tang and H. Zhou and P. Banerjee},
    title = {Leakage power optimization with dual-{Vth} libraray in high-level synthesis},
    booktitle = {DAC},
    year = {2005}
}

@inproceedings{
HLS:Mohanty07,
    author = {S.P. Mohanty and E. Kougianos},
    title = {Simultaneous power fluctuation and average power minimization during nano-{CMOS} behavioral synthesis},
    booktitle = {VLSID},
    year = {2007}
}

@inproceedings{
HLS:Srivastava07,
    author = {A. Srivastava and T. Kachru and D. Sylvester},
    title = {Low-power-design space exploration considering process variation using robust optimization},
    booktitle = {IEEE TCAD},
    year = {2007}
}

@inproceedings{
HLS:Srivastava04,
    author = {A. Srivastava and D. Sylvester},
    title = {Minimizing total power by simultaneous {Vdd-Vth} assignment},
    booktitle = {IEEE TCAD},
    year = {2004}
}

@inproceedings{
HLS:Kim03,
    author = {N. Kim and et al.},
    title = {Leakage current: {Moore's Law} meets static power},
    booktitle = {IEEE Computer},
    year = {2003}
}

@inproceedings{
HLS:Shiue00,
    author = {W. Shiue and C. Chakrabarti.},
    title = {Low power scheduling with resources operating at multiple voltages},
    booktitle = {IEEE Transactions on Circuits and Systems},
    year = {2000}
}

@inproceedings{
HLS:Kulkarni04,
    author = {S. Kulkarni and \emph{et al.}},
    title = {A new algorithm for improved {Vdd} assignment in low power dual {Vdd} systems},
    booktitle = {ISLPED},
    year = {2004}
}

@inproceedings{
HLS:Tawfik07,
    author = {S. Tawfik and V. Kursun},
    title = { Multi-{Vth} Level Conversion Circuits for Multi-{VDD} Systems},
    booktitle = {ISCAS},
    year = {2007}
}

@book{
op-book,
   Author = {E. Aarts and J. K. Lenstra},
   Title = {Local Search in Combinatorial Optimization},
   Publisher = {Princeton University Press},
      Year = {2003}
}

@inproceedings{
HLS:Raghunathan95,
    author = {Raghunathan, A. and  Jha, N.K.},
    title = { An iterative improvement algorithm for low power data pathsynthesis},
    booktitle = {ICCAD},
    year = {1995}
}

@inproceedings{
HLS:Ishihara04,
    author = {F. Ishihara and F. Sheikh and B. Nikolic},
    title = {Level conversion for dual-supply systems},
    booktitle = {IEEE TVLSI},
    year = {2004}
}

@inproceedings{
HLS:Wolfgang09,
    author = {W. Rosenstiel},
    title = {Automated Synthesis and Verification of Embedded Systems: Wishful Thinking or Reality?},
    booktitle = {Proceedings of ASPDAC},
    year = {2009}
}

@book{
HLS:newbook,
    author = {P. Coussy and A. Morawiec },
    title = {High-Level Synthesis: From Algorithm to Digital Circuit },
    publisher = {Springer},
    year = {2009}
}

@inproceedings{UsamiI00,
  author    = {K. Usami and M. Igarashi},
  title     = {Low-power design methodology and applications utilizing
               dual supply voltages},
  booktitle = {ASPDAC},
  year      = {2000},
}

@inproceedings{Shin09,
  author    = {I. Shin, S. Paik, and Y. Shin},
  title     = {Register allocation for high-level synthesis using dual supply voltages},
  booktitle = {DAC},
  year      = {2009},
}

@inproceedings{Keys75,
  author    = {R. Keys},
  title     = {Physical limits in digital electronics},
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  year      = {1975},
}

@inproceedings{Zhai05,
author = {Zhai, Bo and Hanson, Scott and Blaauw, David and Sylvester, Dennis},
title = {Analysis and mitigation of variability in subthreshold design},
booktitle = {ISLPED '05: Proceedings of the 2005 international symposium on Low power electronics and design},
year = {2005},
isbn = {1-59593-137-6},
pages = {20--25},
location = {San Diego, CA, USA},
doi = {http://doi.acm.org/10.1145/1077603.1077610},
publisher = {ACM},
address = {New York, NY, USA},
}

@inproceedings{Meterelliyoz10,
  author    = {Mesut Meterelliyoz and Ashish Goel and Jaydeep Kulkarni and Kaushik Roy},
  title     = {Accurate Characterization of Random Process Variations Using a Robust Low-Voltage High-Sensitivity Sensor Featuring Replica-Bias Circuit},
  booktitle = {ISSCC},
  year      = {2010},
}

@INPROCEEDINGS{Beaulieu94,
author={Beaulieu, N.C. and Abu-Dayya, A.A. and McLane, P.J.},
journal={IEEE International Conference on Communications},
title={Comparison of methods of computing lognormal sum distributions and outages for digital wireless applications},
year={1994},
month={may},
volume={},
number={},
pages={1270 -1275 vol.3},
keywords={accuracy;computational effort;cumulants matching approach;dB spread;digital wireless applications;distribution function;lognormal random variables;lognormal sum distributions;outages;wireless transmission;digital radio;higher order statistics;log normal distribution;mobile radio;},
doi={10.1109/ICC.1994.368899},
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@inproceedings{Chen98,
 author = {Chen, Chung-Ping and Chu, Chris C. N. and Wong, D. F.},
 title = {Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation},
 booktitle = {ICCAD '98: Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design},
 year = {1998},
 isbn = {1-58113-008-2},
 pages = {617--624},
 location = {San Jose, California, United States},
 doi = {http://doi.acm.org/10.1145/288548.289097},
 publisher = {ACM},
 address = {New York, NY, USA},
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@INPROCEEDINGS{Koh00,
author={Liqiong Wei and Kaushik Roy and Cheng-Kok Koh},
journal={Proceedings of the Custom Integrated Circuits Conference.},
title={Power minimization by simultaneous dual-{Vth} assignment and gate-sizing},
year={2000},
month={},
volume={},
number={},
pages={413 -416},
keywords={CMOS circuits;dynamic power dissipation;gate-sizing;leakage power reduction;low voltage circuits;optimization;power dissipation model;power minimization;simultaneous dual-Vth assignment;switching activities;CMOS integrated circuits;circuit optimisation;integrated circuit modelling;leakage currents;low-power electronics;},
doi={10.1109/CICC.2000.852697},
ISSN={},}

@INPROCEEDINGS{Karnik02,
author={Karnik, T. and Yibin Ye and Tschanz, J. and Liqiong Wei and Burns, S. and Govindarajulu, V. and De, V. and Borkar, S.},
journal={Design Automation Conference}, title={Total power optimization by simultaneous dual-{Vt} allocation and device sizing in high performance microprocessors},
year={2002},
month={},
volume={},
number={},
pages={486 -491},
keywords={Lagrangian relaxation based tool;VLSI;computation runtime;design automation solutions;design migration;device sizing;heuristic iterative optimization flow;high performance microprocessors;iSTATS;iterative nature;simultaneous dual-Vt allocation;total power optimization;circuit optimisation;integrated circuit design;iterative methods;logic CAD;microprocessor chips;},
doi={},
ISSN={},}

@ARTICLE{Pant01,
author={Pant, P. and Roy, R.K. and Chattejee, A.},
journal={ IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, title={Dual-threshold voltage assignment with transistor sizing for low power {CMOS} circuits},
year={2001},
month={apr},
volume={9},
number={2},
pages={390 -394},
keywords={CMOS;device sizing;digital random logic;dual-threshold voltage assignment;dynamic power consumption;low power CMOS circuits;static power consumption;supply voltage reduction;total power dissipation;transistor sizing;CMOS logic circuits;VLSI;circuit CAD;circuit optimisation;integrated circuit design;logic CAD;low-power electronics;},
doi={10.1109/92.924061},
ISSN={1063-8210},}

@INPROCEEDINGS{Siri99,
author={Sirichotiyakul, S. and Edwards, T. and Chanhee Oh and Jingyan Zuo and Dharchoudhury, A. and Panda, R. and Blaauw, D.},
journal={Design Automation Conference}, title={Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing},
year={1999},
month={},
volume={},
number={},
pages={436 -441},
keywords={MOS digital circuit;circuit sizing;dominant leakage states;dual Vt process;low power design;optimization;stand-by power minimization;state probability;threshold voltage;MOS digital integrated circuits;circuit optimisation;integrated circuit design;leakage currents;low-power electronics;minimisation;},
doi={10.1109/DAC.1999.781356},
ISSN={},}

@INPROCEEDINGS{Boning00,
    author = {Duane S. Boning and Sani Nassif},
    title = {Models of Process Variations in Device and Interconnect},
    booktitle = {Design of High Performance Microprocessor Circuits},
    year = {2000},
    publisher = {IEEE Press}
}

@ARTICLE{Pelgrom89,
author={Pelgrom, M.J.M. and Duinmaijer, A.C.J. and Welbers, A.P.G.},
journal={Solid-State Circuits, IEEE Journal of}, title={Matching properties of {MOS} transistors},
year={1989},
month={oct},
volume={24},
number={5},
pages={ 1433 - 1439},
keywords={ MOS transistors; current factor; long-distance matching; matching properties; model; rotation of devices; substrate factor; threshold voltage; transistor area; transistor orientation; transistor separation; MOS integrated circuits; insulated gate field effect transistors; semiconductor device models;},
doi={10.1109/JSSC.1989.572629},
ISSN={0018-9200},}

@inproceedings{Kwong06,
 author = {Kwong, Joyce and Chandrakasan, Anantha P.},
 title = {Variation-driven device sizing for minimum energy sub-threshold circuits},
 booktitle = {ISLPED '06: Proceedings of the 2006 international symposium on Low power electronics and design},
 year = {2006},
 isbn = {1-59593-462-6},
 pages = {8--13},
 location = {Tegernsee, Bavaria, Germany},
 doi = {http://doi.acm.org/10.1145/1165573.1165578},
 publisher = {ACM},
 address = {New York, NY, USA},
 }

@INPROCEEDINGS{Shin10,
    author = {Jinuk Luke Shin and Kenway Tam and Dawei Huang and Bruce Petrick},
    title = {A 40nm 16-Core 128-Thread {CMT SPARC SoC} Processor},
    booktitle = {Proceedings of ISSCC},
    year = {2010},
}

@INPROCEEDINGS{Kurd10,
    author = {Nasser A. Kurd and Subramani Bhamidipati and Christopher Mozak and Jeffrey L. Miller and Timothy M. Wilson and Mahadev Nemani and Muntaquim Chowdhury},
    title = {Westmere: A Family of 32nm IA Processors},
    booktitle = {Proceedings of ISSCC},
    year = {2010},
}

@INPROCEEDINGS{Chen10,
author={Yibo Chen and Xie, Yuan and Yu Wang and Takach, Andres},
booktitle={ASP-DAC},
title={Parametric yield driven resource binding in behavioral synthesis with {multi-Vth/Vdd} library},
year={2010},
}
